Modern multiprocessor memory

It's amazing how sophisticated the implementation of a modern multiprocessor memory architecture has become.

I was recently looking for some good links to give to a friend to help him get a high-level understanding of the complexity of these modern systems, and came across these.

• The Common System Interface: Intel’s Future Interconnect

  The design goals for CSI are rather intimidating. Roughly 90% of all servers sold use four or fewer sockets, and that is where Intel faces the greatest competition. For these systems, CSI must provide low latency and high bandwidth while keeping costs attractive. On the other end of the spectrum, high-end systems using Xeon MP and Itanium processors are intended for mission critical deployment and require extreme scalability and reliability for configurations as large as 2048 processors, but customers are willing to pay extra for those benefits. Many of the techniques that larger systems use to ensure reliability and scalability are more complicated than necessary for smaller servers (let alone notebooks or desktops), producing somewhat contradictory objectives. Consequently, it should be no surprise that CSI is not a single implementation, but rather a closely related family of implementations that will serve as the backbone of Intel’s architectures for the coming years.

• An Introduction to the Intel QuickPath Interconnect

  The Intel QuickPath Interconnect is a high-speed, packetized, point-to-point interconnect used in Intel’s next generation of microprocessors first produced in the second half of 2008. The narrow high-speed links stitch together processors in a distributed shared memory-style platform architecture.

• Intel QuickPath Architecture

  Of particular importance to the performance of a system is the speed at which a microprocessor and its execution cores can access system memory (in addition to internal cache). In a multi-processor system not only is the actual access to data important, but also the multi-processor communication required to ensure memory coherency (also called snoop traffic).

• Sandy Bridge-EP Launches

  Sandy Bridge-EP is the first processor with QPI 1.1 for coherent communication. QPI 1.1 has several key architectural changes, primarily shifting from source snooping to a home snooping coherency protocol. Home snooping was already used by Intel’s Itanium and 4-socket x86 servers, so the entire product portfolio now uses the same basic techniques.

Are there better descriptions or other papers I should be reading? Let me know!